Networks on chips [editorial]

Networking has been proven in the computer system arena to be an extremely effective means of managing parallel communication flows in distributed systems. By distilling the most applicable concepts from this domain and by applying them in a way that suits the constraints of semiconductor design, Networks-on-chip (NoCs) have been proposed as the communication backbone for large-scale integrated systems. NoCs are already used for Multi-Processor Systems-on-Chip (MPSoC) in the embedded systems domain, where multiple programmable processors are accompanied by large numbers of hardware accelerators. NoC-based SoCs can achieve higher performance at lower cost, in combination with higher programmability. Designers of high-performance microprocessors plan to take full advantage of this disruptive interconnect technology, as early research-oriented prototypes of many-core microprocessors like the Intel Polaris chip prove. For both domains, latency minimisation and/or tolerance remain a big challenge. Currently, the superiority of NoCs with respect to state-of-the-art interconnect fabrics, mostly in terms of operating speed and scalability, is well understood, NoCs being competitive already in a 130 nm technology node. Even the implications of bringing NoCs to a 65 nm technology node have been investigated. Moreover, guiding principles for the design of basic network building blocks (switches and network interfaces) are consolidated. These achievements can be considered a major milestone in network-on-chip research. At this time, it is becoming apparent that removing roadblocks for an effective NoC utilisation in future industrial products implies not only a knowledge of basic architecture design techniques and physical design principles, but also a deeper understanding of cross-layer design trade-offs. NoC design should be integrated into a cooperative design platform filling the gap between the design layers (from application to physical design) and enforcing cross-layer design and optimisation. This Special Issue serves the purpose of collecting timely and selected research contributions on this new frontier of NoC design. The specific focus will be on the architecture layer, while trying to capture how the awareness of the upper and lower design layers affects NoC architecture design. In this direction, the network architecture might be configured and its parameters tuned based on the knowledge of application requirements. For instance, if we are designing a NoC specifically for a set of applications, then it is desirable to determine minimal sizes for the network buffers, as they are major contributor to NoC power and silicon area, while meeting application real time requirements. In 'Enabling Application-Level Performance Guarantees in Network-Based Systems on …